The present invention relates to a semiconductor device using a TFT (thin film transistor) provided on an insulating substrate such as glass substrate, and to a process for fabricating the same. More particularly, the present invention relates to a semiconductor device usable for a liquid crystal display device of an active matrix type, and to a process for fabricating the same.
The semiconductor devices comprising TFTs on insulating substrates (such as glass substrates) include liquid crystal display devices of active matrix type and image sensors using the TFTs for driving pixels. In general, thin-film silicon semiconductors can be roughly classified into two types: one is an amorphous silicon semiconductor (a-Si), and the other is a crystalline silicon semiconductor. An amorphous silicon semiconductor can be fabricated relatively easily by a vapor phase process at a low temperature, and by mass production. Accordingly, amorphous silicon semiconductors are employed most generally in the TFTs of the devices above. However, in order to obtain a high speed operation, it has been strongly desired to establish a process for fabricating a TFT utilizing a crystalline silicon semiconductor, because amorphous silicon semiconductors are still inferior to the crystalline silicon semiconductors with respect to physical properties such as the electrical conductivity. Known crystalline semiconductors include polycrystalline silicon, microcrystalline silicon, amorphous silicon partly comprising crystalline components, and semi-amorphous silicon which exhibits an intermediate state between crystalline silicon and amorphous silicon.
A thin film of a crystalline silicon semiconductor enumerated above can be fabricated by any of the following known processes:
(1) A process which comprises directly depositing a crystalline film in the step of film deposition; PA0 (2) A process which comprises depositing an amorphous semiconductor film, and then irradiating a laser beam to the film to obtain a crystallized semiconductor by taking advantage of the laser beam energy; and PA0 (3) A process which comprises depositing an amorphous semiconductor film, and then applying thermal energy to crystallize the film to obtain a crystalline semiconductor.
With respect to the above first process, it is technologically difficult to form a uniform film having favorable semiconductor properties on the entire surface of the substrate because the crystallization proceeds simultaneously with the film deposition. Furthermore, a thick film process is indispensable in this case to obtain crystalline silicon composed of large grains. Moreover, this process is uneconomical, because it excludes the use of a low cost glass substrate due to the presence of a film deposition step which requires a temperature as high as 600.degree. C. or even higher.
The second process utilizes the crystallization phenomena in a melting and solidification process. Thus, although the grain size of the obtained film is relatively small, the grain boundary thereof is favorably treated with to provide a high quality crystalline silicon film. However, concerning a process employing the most commonly used laser at present, i.e., an excimer laser, there can be found problems to be overcome. Firstly, considering that a laser beam can irradiate too small an area at a time, the process is still disadvantageous in that it can only afford a low throughput. Furthermore, the laser is not sufficiently stable to cover the entire surface of a large area substrate with a uniform film. Thus, it can be safely said that this process awaits a further advanced technology.
The third process is superior to the above first second processes concerning its applicability to the deposition of large area films. However, it also requires a thermal treatment at a high temperature of 600.degree. C. or even higher during the crystallization. This process also excludes the use of inexpensive glass substrates, and moreover, yields a low throughput. Thus, it is required to overcome the conflicting problems of lowering the film deposition temperature and crystallizing the film in a short period of time. Furthermore, this process is based on a solid phase crystallization phenomena. Accordingly, the crystal grains grow in parallel with the substrate to occasionally provide large grains having a diameter as large as some micrometers. However, on the other hand, grains grow and collide with each other to form the boundaries. The grain boundaries thus formed are the main cause of lowering the mobility of a TFT, because these grain boundaries function as trap levels for the carriers.
To overcome the various problems above, a process for fabricating a thin film of crystalline silicon is proposed in Japanese patent application No. 5-218156 (which was published (laid-open) as a Publication No. 7-58338 on Mar. 3, 1995). This process enables a low crystallization temperature and a short-time processing at the same time, and it minimizes the influence of the grain boundaries.
In the process above, an impurity metal element such as nickel (Ni) is incorporated in an amorphous silicon film to provide nuclei for the crystallization. By thus adding an impurity metal element, the rate of nucleation in the initial period of crystallization as well as that of nucleus growth in the later stages of crystallization can be considerably increased as to provide a film having a sufficiently high crystallinity by effecting heat treatment at a temperature of 580.degree. C. or lower for a duration of about 4 hours. The mechanism of the nucleation and growth of nuclei in this process is yet to be made clear, however, assumably, the impurity metal elements function as the nuclei for generating nuclei in an earlier stage, and then as a catalyst to accelerate the crystal growth.
By selectively providing impurity metal elements on a part of the substrate, a crystalline silicon film and an amorphous silicon film can be formed selectively on the same substrate. By further continuing the heat treatment, the grain growth extends in a lateral direction (i.e., a direction in parallel with the surface of the substrate) from the crystallized portion into which the metal impurity is incorporated selectively to an adjacent region in which the metal is not directly added. This portion in which crystal growth occurred in the lateral direction is referred to simply hereinafter as a "laterally grown portion". In the laterally grown portion, needle-like or columnar crystals are found to extend in parallel with the substrate and in a direction of crystal growth. No grain boundaries are found in the direction of crystal growth. Thus, by arranging a channel region of a TFT along with the laterally grown portion, a high performance TFT can be realized.
For instance, a channel portion of a TFT can be fabricated in a manner illustrated in FIGS. 5(A) and 5(B). FIGS. 5(A) and 5(B) are each a planar view of a TFT utilizing a laterally grown portion. The fabrication process comprises depositing a mask film comprising a silicon dioxide film and the like on the surface of a thin film of amorphous silicon formed on the entire surface of the substrate, and an impurity metal element is introduced to the thin film of amorphous silicon after opening a window 500 in the mask film to incorporate impurities therethrough. By applying a heat treatment at about 550.degree. C. for a duration of about 4 hours, the region 500 into which an impurity metal element is added undergoes crystallization while leaving over the rest of the portions in the amorphous state. By further continuing the heat treatment for about 8 hours, the region 500 into which impurity metal element is added grows outward in the lateral direction 501 to provide a laterally grown portion 502. A TFT can be fabricated by using the laterally grown portion 502. By providing a source region 503, a channel region 504, and a drain region 505 in the laterally grown portion 502 in an arrangement illustrate in FIG. 5(A), the direction of the carrier movement can be aligned with the direction of the crystal growth 501. Accordingly, a high mobility TFT having no grain boundaries in the direction of carrier movement can be implemented.
Furthermore, a TFT having a high ON/OFF ratio can be fabricated by providing a source region 503, a channel region 504, and a drain region 505 with respect to the laterally grown portion 502 in an arrangement illustrate in FIG. 5(B). That is, grain boundary portions can be eliminated from the region of electric field-concentrated regions provided to the end portions of the drain, and the density of grain boundary traps at the front end portions of the drain can be reduced. The grain boundary traps are found to be the cause for increasing leak current when the TFT is in an OFF operation.
The technology proposed in Japanese patent application No. 5-218156 enables the formation of not only a high performance TFT, but also various types of TFTs fabricated on a same substrate.
Although the technology disclosed in the above Japanese patent application No. 5-218156 is very effective, there are still several problems to be overcome.
A sufficiently long distance for a lateral growth, such as to cover at least the channel region of a TFT, is necessary to apply the technology. Because the region which is left over after the lateral growth remains as an amorphous silicon film, if lateral growth occurs only insufficiently, laterally grown crystalline silicon film and an amorphous silicon film will remain mixed in the channel region as to greatly impair the characteristics of the TFT. Furthermore, even if the channel would be formed by a laterally grown crystalline silicon, if the so-called contact region corresponding to a source or a drain region should remain as an amorphous silicon film, the resistance in the contact region would increase as to make it impossible to realize sufficiently high TFT characteristics.
In the process disclosed in Japanese patent application No. 5-218156, an amorphous silicon (a-Si) film deposited by plasma-assisted CVD (referred to simply hereinafter as "plasma CVD") is used as a starting film for the laterally grown crystalline silicon film. A plasma CVD process is currently put into practice in a process for a-Si TFT, because it is suitable for mass production of a-Si films under a low temperature. However, in view of the applicability thereof to the fabrication of a starting film for a crystalline silicon film, an a-Si film generates nuclei at a relatively high rate. Hence it is difficult to obtain a high quality crystalline silicon film from the a-Si film by effecting crystallization in an ordinary solid phase growth method without adding any impurity metal element.
In case of adding an impurity metal element as described in the technology disclosed in Japanese patent application No. 5-218156, the crystallization of a region into which the impurity metal element is directly added depends only on the concentration of the metal element added therein, and not on the type of the starting a-Si film. However, in a laterally grown portion, the nucleation rate in the a-Si film in the direction of lateral growth is found as a problem to be considered. That is, when an a-Si film deposited by plasma CVD process should be used as the starting film for fabricating a laterally grown crystalline silicon film, the lateral growth would be hindered by a general crystal growth which occurs from a naturally generated nuclei in the a-Si region. Accordingly, the lateral growth would not occur over a sufficiently long distance as to cover the channel region of a TFT with a laterally grown crystalline silicon film.
Furthermore, in a crystalline silicon TFT obtained by a conventional process of solid phase crystallization, a step of solid phase crystallization is effected at a maximum temperature of the process before carrying out the step of photolithography (isolation of devices on a silicon film). However, in a TFT using a laterally grown portion according to the technology disclosed in Japanese patent application No. 5-218156, a first step of photolithography (perforation of mask film to add impurity metal elements into the amorphous silicon film through the perforated holes) must be effected before the step of crystallization.
The most generally used 7059 glass (a product of Corning Corp.) undergoes deformation at a temperature of 593.degree. C. Accordingly, it cannot resist to a conventional solid phase crystallization process without being deformed, because the process employs a temperature of 600.degree. C. or higher. In particular, even larger displays are required in the present day liquid crystal display devices. Those devices keenly demand their implementation using larger glass substrates. If a step of photolithography should be effected on such large-area glass substrates before applying the step of thermal crystallization, shrinking and deformation which occur in a glass substrate during the step of thermal crystallization impair the precision in the later mask aligning step to occasionally make the fabrication unfeasible.
That is, in accordance with the technology disclosed in Japanese patent application No. 5-218156 above, although a sufficiently long distance for lateral crystal growth as to cover the channel region of a TFT is obtained in some of the devices with reference to FIG. 6, there may be cases in some of the devices in which it is found impossible to form a channel region 504 in the laterally grown portion 502 due to the mismatch attributed to the shrinking of the substrate which occurs after the step of thermal crystallization. Furthermore, there are cases in which the channel region 504 is afforded by using the laterally grown portion 502, but in which the source/drain region 503/505 remain as they are in the state of amorphous silicon film due to the lateral growth which occurs over an insufficient length.
More specifically, a Corning 7059 glass shrinks at 200-400 ppm by subjecting it to a heat treatment at a temperature of 580.degree. C. for a duration of 16 hours. In a square substrate 100 mm.times.100 mm in area, the absolute shrinkage is found to be in a range of from 20 to 40 .mu.m. Thus, by extending the distance of lateral growth to a length of 40 .mu.m or longer, a margin for the shrinkage of the glass substrate can be obtained. It is then possible to fabricate the channel region of a TFT in the laterally grown portion. In a square substrate 500 mm.times.500 mm in area, however, the absolute shrinkage amounts to fall in a range of from 100 to 200 .mu.m. It can be readily understood that an a-Si obtained by a conventional plasma CVD process is no longer applicable as a starting film in case such a long shrinkage margin is required for lateral growth. Thus, it can be understood that even though a high performance TFT should be partly obtained by the technology disclosed in Japanese patent application No. 5-218156 alone, it is practically unfeasible to uniformly form high performance TFTs exhibiting the same characteristics over a large area substrate.
Furthermore, from the viewpoint of the object of effecting the lateral crystal growth, which is to make the crystals to grow in a single direction, it has been found difficult to obtain a high quality crystalline silicon film composed of one-dimensionally grown crystals when an a-Si film fabricated by plasma CVD process is used as the starting film. This is attributed to the branching in the direction of crystal growth that occurs due to the influence of the nuclei which generate inherently during the process of crystal growth.
This phenomena is particularly distinct when the heat treatment is effected at a temperature of about 600.degree. C. or for a long duration enduring for several tens of hours with an aim to obtain a longer distance of lateral growth. That is, by increasing the length of lateral growth in an a-Si film obtained by plasma CVD having a high rate of nucleation, a plurality of branches are observed to occur at the front of the direction of crystal growth. Accordingly, a high quality crystalline silicon film as desired cannot be obtained in such cases.
Branching occurs in the laterally grown portions in the direction of crystal growth due to not only the nucleation in the a-Si region as described above, but also the presence of impurities such as oxygen, carbon, nitrogen, and other metallic elements that are incorporated in the a-Si film. Oxygen is particularly problematic, and if oxygen is incorporated at an amount higher than a certain content, defects generate from the oxygen clusters as to interfere the crystal growth. That is, residual oxygen inside an a-Si film hinders lateral growth as to induce branching. As described in J. Appl. Phys., 68 (1990) p. 1029, a film deposited by plasma CVD process contains oxygen at a concentration as high as 3.times.10.sup.19 cm.sup.-3 or even higher, as well as carbon and nitrogen which amount to a relatively high concentration of 3.times.10.sup.18 cm.sup.-3 or higher and 1.times.10.sup.18 cm.sup.-3 or higher, respectively.
In the case of using a plasma CVD process, moreover, the metallic elements contained in the electrode are taken up by the film during the deposition thereof. Thus, the content of the impurity metal elements in the film becomes relatively high as compared with that in a film deposited by other thermal CVD processes. Thus, it can be understood that, if a film deposited by a plasma CVD process should be used as the starting film for a laterally grown crystalline silicon film, branching would occur with a higher probability from the viewpoint of impurity content thereof. Accordingly, it can be understood that a low quality crystalline silicon film containing crystal defects in a high concentration results from a film deposited by plasma CVD.